A NOVEL FRACTIONAL-N PLL BASED ON A SIMPLE REFERENCE MULTIPLIER

作者：Pu Xiao^*; Nagaraj Krishnaswamy; Abraham Jacob; Thomsen Axel

来源：Journal of Circuits, Systems, and Computers, 2012, 21(6): 1240010.

DOI：10.1142/S0218126612400105

• PLL
• synthesizer
• fractional-N
• delta sigma
• noise shaping

A wide loop bandwidth in fractional-N PLL is desirable for good jitter performance. However, a wider bandwidth reduces the effective oversampling ratio between update rate and loop bandwidth, making quantization error a much bigger noise contributor. A successful implementation of a wideband frequency synthesizer is in managing jitter and spurious performance. In this paper we present a new PLL architecture for bandwidth extension. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single reference cycle and utilized for phase update, thereby effectively forming a reference multiplier. This enables a higher oversampling ratio for better quantization noise shaping and makes a wideband fractional-N PLL possible.

• 出版日期2012-10