A Low-Jitter Full-Rate 25-Gb/s CDR for 100-Gb/s Optical Interconnects in 0.13-m SiGe BiCMOS

作者：Zhang, Zhen; Chen, Yingmei^*; Li, Jiquan; Wang, Hui; Gao, Chenyang

来源：Fiber and Integrated Optics, 2017, 36(4-5): 172-180.

DOI：10.1080/01468030.2017.1364803

• Bang-bang phase detector
• clock and data recovery
• heterojunction bipolar transistor
• phase-locked loop

A low-jitter full-rate 25-Gb/s clock and data recovery (CDR) chip for 100-Gb/s optical interconnects is proposed. Fabricated in 0.13-m SiGe BiCMOS technology, the chip is implemented in a third-order type-II bang-bang phase-locked loop (BBPLL) topology. To achieve optimal switching speed, all SiGe heterojunction bipolar transistors (HBTs) in high-speed blocks are biased at peak f(T) current density. Transistors are sized by carefully balancing speed versus power consumption. Emitter-coupled logic (ECL) and current-mode logic (CML) are employed in logic components. Compared with conventional spiral inductors, the employment of RF transmission lines in resonators of the VCO reduces the area of the VCO and, thus, the whole chip, without sacrificing the performance. The core circuits occupy an area of 0.48 mm(2). The CDR recovers a clock with an rms jitter of 750 fs and a peak-to-peak jitter only of 3.46 ps.

• 出版日期2017
• 单位东南大学