A 1.9-3.8 GHz Delta Sigma Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency

作者：Shin Jaewook^*; Shin Hyunchol

来源：IEEE Journal of Solid-State Circuits, 2012, 47(3): 665-675.

DOI：10.1109/JSSC.2011.2179733

• Auto-calibration
• constant loop bandwidth
• fractional-N frequency synthesizer
• loop bandwidth calibration
• PLL
• VCO frequency calibration

A fast and high-precision all-digital automatic calibration circuit that is highly suited for Delta Sigma fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock time over an octave tuning range. A high-speed frequency-to-digital converter (FDC) measures VCO frequency on-chip with a sub-f(REF) frequency resolution of f(REF)/k in a time period of k. T-REF. The on-chip detected VCO frequency is then used for calibrating the loop bandwidth and the VCO frequency. The loop bandwidth calibration circuit measures the VCO gain K-VCO and uses it to precisely control the charge pump current, hence making the loop bandwidth constant. For the VCO frequency calibration, a minimum error code finding block significantly enhances the calibration accuracy by finding the truly closest code to the target frequency. Moreover, this method does not need to activate Delta Sigma modulator to achieve sub-f(REF) calibration resolution, which makes this technique much accurate and faster than the conventional ones. A 1.9-3.8 GHz Delta Sigma fractional-N synthesizer is implemented in 0.13 mu m CMOS, demonstrating that the loop bandwidth calibration is completed in 1.1-6.0 mu s with +/-2% accuracy and the VCO frequency calibration is completed in 1.225-4.025 mu s, all across the entire octave tuning range.

• 出版日期2012-3