A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

作者：Glittas Antony Xavier^*; Sellathurai Mathini; Lakshminarayanan Gopalakrishnan

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(6): 2402-2406.

DOI：10.1109/TVLSI.2015.2504391

• Bit reversal
• bit reversed order
• fast Fourier transform (FFT)
• multipath delay commutator (MDC) FFT
• normal order

Nowadays, many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this brief presents a novel pipelined FFT processor for the FFT computation of two independent data streams. The proposed architecture is based on the multipath delay commutator FFT architecture. It has an N/2-point decimation in time FFT and an N/2-point decimation in frequency FFT to process the odd and even samples of two data streams separately. The main feature of the architecture is that the bit reversal operation is performed by the architecture itself, so the outputs are generated in normal order without any dedicated bit reversal circuit. The bit reversal operation is performed by the shift registers in the FFT architecture by interleaving the data. Therefore, the proposed architecture requires a lower number of registers and has high throughput.

• 出版日期2016-6