An efficient CSA architecture for montgomery modular multiplication

作者：Zhang Yuan Yang^*; Li Zheng; Yang Lei; Zhang Shao Wu

来源：Microprocessors and Microsystems, 2007, 31(7): 456-459.

DOI：10.1016/j.micpro.2006.12.003

• Montgomery algorithm
• addition
• CSA
• FPGA

Montgomery multipliers of carry save adder (CSA) architecture require a full addition to convert the carry save representation of the result into a conventional form. In this paper, we reuse the CSA architecture to perform the result format conversion, which leads to small area and fast speed. The results of implementation on FPGAs show that the new Montgomery multiplier is about 113.4 Mbit/s for 1024-bit operands at a clock of 114.2 MHz.

• 出版日期2007-11-1
• 单位中国人民解放军信息工程大学