Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops

作者：Arakali Abhijith^*; Gondi Srikanth; Hanumolu Pavan Kumar

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2010, 57(11): 2880-2889.

DOI：10.1109/TCSI.2010.2052507

• Charge pump
• frequency divider
• loop filter
• phase-frequency detector
• phase-locked loops
• supply noise
• VCO buffer
• voltage regulator

Supply noise affects the jitter performance of ring oscillator-based phase-locked loops (PLLs) significantly. While the focus of much of the prior art is on supply noise in oscillators, this paper illustrates that supply noise in other building blocks also contribute significantly to PLL output jitter. Analytical expressions for supply-noise sensitivities are derived for each of the circuit blocks used in the PLL and insight into the mechanism through which supply noise appears at the PLL output is provided. Efficient supply-regulation schemes that combine a split-tuned PLL architecture with an optimized low-dropout regulator to achieve better than -22 dB of worst case supply-noise sensitivity for the whole PLL are presented. Fabricated in a 0.18 mu m digital CMOS process, the prototype PLL occupies an area of 0.18 mu m and operates from a 1.8 V supply. At 1.5 GHz, the total power consumption is 3.3 mW, of which 0.54 mW is consumed in the regulators. The measured output peak-to-peak jitter is 33 ps and 41 ps with no supply noise and with a 100-mV amplitude supply noise tone injected at the worst case noise frequency, respectively.

• 出版日期2010-11