An Accelerator for Decoding Market Data Based on FPGA

作者：Dou, Yuhao; Zhou, Yisu; Xin, Bo^*

来源：Journal of Circuits, Systems, and Computers, 2019, 28(3): 1950050.

DOI：10.1142/S0218126619500506

• Low latency
• decoding
• FPGA
• FIX
• FAST

In securities trading, low latency helps investors take the leading position in the market. Conventionally, market data is decoded with software running on general computers. However, the serial structure of software and complex operating system scheduling cause high latency. This paper designs an accelerator for decoding market data based on field-programmable gate array (FPGA). We propose a pipeline in the accelerator, where every part works independently and parallelly. Furthermore, we present a mechanism for encoding templates, which avoids reconstructing the accelerator and decreases the cost when the template is renewed. We evaluate this accelerator with real Financial Information eXchange (FIX) messages and FIX Adapting for Streaming (FAST) templates, attaining an average latency of 447ns.

• 出版日期2019-3
• 单位南京大学