A 28Gbps 4x4 switch with low jitter SerDes using area-saving RF model in 0.13 mu m CMOS technology

作者：Hsu Yu Hao; Lu Ming Hao; Yang Ping Lin; Chen Fan Ta; Li You Hung; Kao Min Sheng; Lin Chih Hsing; Chiu Ching Te; Wu Jen Ming; Hsu Shuo Hung; Hsu YarSun

来源：IEEE International Symposium on Circuits and Systems, 2008-05-18 to 2008-05-21.

In this paper, we present a 7Gbps/Ch quad SerDes integrated with a 4x4 load-balanced switch fabric circuit for high speed networking applications. To achieve high-speed and low area, we propose an area-saving RF model device for the SerDes design. The area-saving RF model has almost the same speed and jitter performance with the RF model but only consumes one half of the area. In our hybrid design of the SerDes architecture, the area-saving RF model mixed with the baseband model can reduce 75% of area compared with the design using only the conventional RF model. The grounded coplanar waveguide (GCPW) type transmission line is also employed to reduce the clock tree skew for the quad SerDes to within 1ps. The total area is 3mmx2.48mm, including the switch fabric, the quad SerDes interface, and a LG-PLL. In our results, each input/output port of the 4x4 switch fabric can achieve 7Gbps data rate, and the overall throughout is 28Gbps.

• 出版日期2008
• 单位清华大学