Area-Efficient Embedded Resistive RAM ( ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT ( VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

作者：Chang Meng Fan^*; Kuo Chia Chen; Sheu Shyh Shyuan; Lin Chorng Jung; King Ya Chin; Chen Frederick T; Ku Tzu Kun; Tsai Ming Jinn; Wu Jui Jen; Chih Yue Der

来源：IEEE Journal of Solid-State Circuits, 2014, 49(4): 908-916.

DOI：10.1109/JSSC.2013.2297417

• BJT
• ReRAM
• sense amplifier.

The design of resistive RAM ( ReRAM) faces two major challenges: 1) cell area versus write current requirements and 2) cell read current () versus read disturbance. This paper proposes ReRAM macros using logic-process-based vertical parasitic-BJT ( VPBJT) switches and a corresponding cell array ( VPBJT-CA), resulting in a 4.5x macro density compared to conventional NMOS-switch ReRAM for given write current requirements. To overcome temperature-dependent fluctuations in the base-emitter voltage difference () of VPBJT, we propose a temperature-aware bitline ( BL) voltage bias ( TABB) scheme to provide current-mode sensing with 4.7x larger and 1.6x faster read speeds. Test results of fabricated 0.18 mu m 1 Mb and 65 nm 2 Mb VPBJT ReRAM macros confirm the efficacy of the temperature-aware, V-BL-R, resulting in sub-5-ns random read access times.

• 出版日期2014-4
• 单位清华大学