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A 0.4-V Subnanowatt 8-Bit1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications
Harikumar Prakash
Wikner J Jacob
Alvandpour Atila
IEEE Transactions on Circuits and Systems II-Express Briefs, 2016, 63(8): 743-747.
This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm(2).
Analog-to-digital converter (ADC); successive approximation register (SAR); ultralow voltage
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