摘要

A scaling-friendly approach for the low-power calibration of oversampled analog-to-digital (A/D) systems is presented. A 22-dB amplifier relaxes the design constraints of the analog front-end (AFE). The integrator non-idealities in the AFE of the sigma-delta (I I") pound ADC are calibrated using a multi-rate polyphase least-mean squares (LMS) algorithm. The proposed half- (f (s)/2) and quarter-rate (f (s)/4) LMS calibration schemes reduce computational complexity and achieve more than 2.5x savings in digital power consumption for low-OSR (over-sampling ratio) Delta I pound ADCs, which require higher adaptive filter orders and sampling frequencies. The proposed scheme can have further applications in serial-link I/O and sub-band echo cancellation architectures.

  • 出版日期2012-12