科研之友
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摘要
The aging effect due to the electromigration (EM) may result in faulty Through-silicon vias (TSVs) and affect the three-dimensional integrated circuits (3D ICs) lifetime. To design a flexible and efficient structure, in this paper, we enhance the region-based design for latent TSV faults, which can adjust the size of the TSV block and TSV redundancy. Experimental results demonstrate that the design can achieve 11.27% and 20.79% reduction of additional delay overhead as compared with router-based design and ring-based scheme, respectively. More importantly, when the target year is 3 years, the design can achieve above 99% reparability for all sizes of TSV blocks. After a given 5-year lifetime, the reparability of the proposed region-based design can still achieve 99% reparability when the TSV size is lower than 16 * 16, which is the best choice by considering RTSV area and delay overhead.
