A 6-bit 2 GS/s ADC in 65 nm CMOS

作者：Wang HaoNan; Wang Tao; Yao YuFeng; Wang Hui; Cheng YuHua

来源：Science China Information Sciences, 2014, 57(6): 069401.

DOI：10.1007/s11432-014-5101-0

• CMOS
• flash ADC
• interpolating
• averaging
• high-speed comparator

A 6-bit 2 GS/s ADC was implemented using a 65 nm digital CMOS technology. The design is based on a single-channel flash ADC architecture, and utilizes interpolating and averaging techniques. A two-stage CML-CMOS high-speed hybrid comparator is designed for optimal speed and power performance. The total power consumption of the converter is 52 mW and the area is 0.24 mm(2). The ADC achieves 42.5 dB SFDR and 5.2 bit ENOB at input frequency of 123 MHz, and at Nyquist frequency 37.67 dB SFDR and 4.9 bit ENOB.

• 出版日期2014-6
• 单位北京大学