Architecture and Network-on-Chip Implementation of a New Hierarchical Interconnection Network

作者：Awal Md Rabiul^*; Rahman M M Hafizur; Nor Rizal Mohd; Sembok Tengku Mohd Bin Tengku; Akhand M A H

来源：Journal of Circuits, Systems, and Computers, 2015, 24(2): 1540006.

DOI：10.1142/S021812661540006X

• Massively parallel computer
• hierarchical interconnection network
• MMN
• static network performance
• network on chip

A Midimew-connected Mesh Network (MMN) is a minimal distance mesh with wrap-around links network of multiple basic modules (BMs), in which the BMs are 2D-mesh networks that are hierarchically interconnected for higher-level networks. In this paper, we present the architecture of the MMN, addressing of node, routing of message, and evaluate the static network performance of MMN, TESH, mesh and torus networks. In addition, we propose the network-on-chip (NoC) implementation of MMN. With innovative combination of diagonal and hierarchical structure, the MMN possesses several attractive features, including constant degree, small diameter, low cost, small average distance, moderate bisection width and high fault tolerant performance than that of other conventional and hierarchical interconnection networks. The simple architecture of MMN is also highly suitable for NoC implementation. To implement all the links of level-3 MMN, only four layers are needed which is feasible with current and future VLSI technologies.

• 出版日期2015-2
• 单位中国人民解放军国防大学