A Fused Floating-Point Four-Term Dot Product Unit

作者：Sohn Jongwook^*; Swartzlander Earl E Jr^*

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2016, 63(3): 370-378.

DOI：10.1109/TCSI.2016.2525042

• Dot product unit
• floating-point arithmetic
• fused floating-point operations
• high-speed computer arithmetic

This paper presents a novel design for a fused floating-point four-term dot product unit. The dot product is one of the most frequently used operations for a wide variety of graphics, digital signal processing (DSP) and statistical applications. The proposed design computes the four-term dot product in a single unit to achieve better performance and accuracy compared to a network of traditional floating-point multipliers and adders, which is referred to as a discrete design. In order to further improve the performance of the fused floating-point four-term dot product unit, a new exponent compare and significand alignment scheme, dual-reduction, early normalization, four-input Leading Zero Anticipation (LZA), and compound addition and rounding are applied. The proposed design is implemented for both single and double precision and synthesized with a 45 nm CMOS standard-cell library. In order to evaluate the improvement of the proposed design, the area, latency, and power consumption are investigated. The proposed design reduces the area, power consumption and latency by about 40% compared to the discrete design.

• 出版日期2016-3