Delta-sigma DAC with jitter-shaper-reducing jitter noise

作者：Watanabe Yuki^*; Saikatsu Satoshi; Yoshino Michitaka; Yasuda Akira

来源：Analog Integrated Circuits and Signal Processing, 2015, 85(2): 243-251.

DOI：10.1007/s10470-015-0600-5

• D/A converter
• Delta-sigma modulator
• Jitter shaper
• Clock jitter

We present a novel delta-sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The jitter shaper is designed for a 0.18 A mu m CMOS and comprises switched capacitor and sample-and-hold circuits. We simulate the DSDAC in MATLAB and design and simulate the complete jitter shaper circuit in SPICE. We predict that the jitter shaper will improve the signal-to-noise ratio by 47.2 dB (MATLAB) up to 24.6 dB (SPICE).

• 出版日期2015-11