A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

作者：Deng Wei^*; Yang Dongsheng; Ueno Tomohiro; Siriburanon Teerachot; Kondo Satoshi; Okada Kenichi; Matsuzawa Akira

来源：IEEE Journal of Solid-State Circuits, 2015, 50(1): 68-80.

DOI：10.1109/JSSC.2014.2348311

• AD-PLL
• CMOS
• DAC
• digital varactor
• dual loop
• edge injection
• gated injection
• injection-locking
• logic synthesis
• low jitter
• low power
• PLL
• PVT
• small area
• standard cell
• synthesizable

This paper presents a fully synthesizable phaselocked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 mu m x 60 mu m layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 mu W DC power.

• 出版日期2015-1