An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 mu m CMOS

作者：Huang Sui^*; Cao Jun; Green Michael M

来源：IEEE Journal of Solid-State Circuits, 2015, 50(9): 2048-2060.

DOI：10.1109/JSSC.2015.2427332

• Analog
• clock-and-data recovery (CDR)
• CMOS
• jitter tolerance
• linear phase detector
• receiver
• referenceless
• wide-band data communication

An 8.2 Gb/s-to-10.3 Gb/s full-rate referenceless CDR in 0.18 mu m CMOS is presented. By realizing an asymmetric phase detector transfer curve, the linear CDR's "single-sided" capture range increases, which allows the Hogge phase detector itself to function as a frequency detector, thus eliminating the need for the reference clock and the separate frequency detector in conventional dual-loop CDRs. Robust frequency and phase acquisition is demonstrated. Furthermore, a new phase adjustment mode is added to further improve the jitter tolerance performance. The measurement results show that with a 10.3 Gb/s 2(31)-1 PRBS input, the random jitter at the output data is 0.336 Ps(rms), and the out-of-band jitter tolerance is 0.34 UIp-p.

• 出版日期2015-9