A cascaded charge-sharing technique for an EDP-efficient match-line design in CAMs

作者：Zhang Jianwei^*; Ye Yizheng; Liu Binda; Lan Jinbao

来源：Chinese Journal of Semiconductors, 2009, 30(6): 065009.

DOI：10.1088/1674-4926/30/6/065009

• CMOS processs
• Content addressable memory
• Match line
• Pre-charge
• Search speed
• Simulation result
• Ternary CAM
• Test-chip

A novel cascaded charge-sharing technique is presented in content-addressable memories (CAMs), which not only effectively reduces the match-line (ML) power by using a pre-select circuit, but also realizes a high search speed. Pre-layout simulation results show a 75.9% energy-delay-product (EDP) reduction of the MLs over the traditional precharge-high ML scheme and 41.3% over the segmented ML method. Based on this technique, a test-chip of 64-word × 144-bit ternary CAM (TCAM) is implemented using a 0.18-μm 1.8-V CMOS process, achieving an 1.0 ns search delay and 4.81 fJ/bit/search for the MLs.

• 出版日期2009