A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA

作者：Zhang Hui^*; Yang Haigang; Wang Yu; Liu Fei; Gao Tongqiang

来源：Chinese Journal of Semiconductors, 2011, 32(4).

DOI：10.1088/1674-4926/32/4/045010

• Clock generator
• Clock signal
• CMOS processs
• Configurable
• Duty cycles
• FPGA design
• Multi-functions
• Operation mode
• Partition methods
• Phase alignment
• PLL
• Power Consumption
• Prototype chip
• Quick start-up
• reconfigurable
• Settling time
• VCO
• Wide tuning range

A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions, respectively. The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable. In order to further improve the accuracy of phase alignment and phase shift, a VCO design based on a novel quick start-up technique is proposed. A new delay partition method is also adopted to improve the speed of the post-scale counter, which is used to realize the programmable phase shift and duty cycle. A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz. The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps, respectively. The settling time is approximately 2 μs.

• 出版日期2011