摘要

A second-order single-bit delta-sigma analog-to-digital converter (ADC) is presented in this paper. An op-amp bias sharing technique is used to reduce the power consumption and active area of the ADC. It achieves 77.5 dB dynamic range over 1 kHz signal bandwidth with an oversampling ratio of 512. The total power consumption of the proposed ADC is 27.1 mu W from a 1.0 V power supply. The prototype chip occupies 0.16 mm(2) using a 0.13 mu m CMOS technology.

  • 出版日期2018-6

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