Design of a fixed-point multiplier based on redundant signed digit

作者：Yao, Ruo-He^*; Xu, Xin-Cai

来源：Journal of South China University of Technology(Natural Science Edition), 2014, 42(3): 27-34.

DOI：10.3969/j.issn.1000-565X.2014.03.005

• Binary converters
• Control signal generator
• Delay reduction
• Design compliers
• Multiplier
• Partial product
• Redundant parallels
• Signed digits

In order to improve the speed and reduce the area of fixed-point multipliers, odd multiple of partial products is represented with the redundant differential based on the Radix-16 redundant parallel multiplier. Then, the correction words of partial products and the partial products are compressed to reduce the number of partial products. Through optimizing the structures of the control signal generator, the Booth decoder and the binary converter, the time delay and the area of the multiplier are further reduced. Finally, the modified multiplier is synthesized by Design Complier with the TSMC 180 nm library, with an area decrement of 8% and a delay reduction of 11% being obtained.

• 出版日期2014-3
• 单位华南理工大学