A Delta-Sigma PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology

作者：Yang Ching Yuan^*; Chang Chih Hsiang; Wong Wen Ger

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2009, 56(1): 51-59.

DOI：10.1109/TCSI.2008.926975

• Fractional divider
• fractional-N phase-locked loop (PLL)
• multiphase signals
• phase interpolation
• spread-spectrum clock generation (SSCG)
• Delta - Sigma modulator

A triangular-modulated spread-spectrum clock generator using a Delta - Sigma-modulated fractional-N phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to implement the modulated fractional counter with increased Delta - Sigma operation speed. In addition, the phase mismatching error in the phase-interpolated PLL with multiphase clocks can be randomized, and finer frequency resolution is achievable. With a frequency modulation of 33 kHz, the measured peak power reduction is more than 11.4 dB under a deviation of +/- 0.37%. Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. After spread-spectrum operation, the measured up-spread and down-spread jitter can achieve 52.59 and 56.79 ps, respectively. The chip occupies 950 x 850 mu m(2) in 0.18-mu m CMOS process and consumes 36 mW.

• 出版日期2009-1
• 单位中国科学院电工研究所