A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time Sigma Delta ADC for a Digital Closed-Loop Class-D Amplifier

作者：Donida Achille^*; Cellier Remy; Nagari Angelo; Malcovati Piero; Baschirotto Andrea

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62(3): 645-653.

DOI：10.1109/TCSI.2014.2373971

• Amplifiers
• analog/digital conversion
• delta-sigma modulation
• mixed analog/digital integrated circuits

This paper presents a continuous-time third-order modulator designed for closing the feedback loop of a digital class-D audio amplifier. The closed-loop digital class-D amplifier fully exploits the potential of the used 40-nm CMOS technology to achieve at the same time the flexibility of digital implementations and the performance of analog solutions. The proposed Sigma Delta modulator consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB dynamic-range (DR) and 72-dB peak signal-to-noise and distortion ratio (SNDR). The active-RC implementation allows the 1.1-V Sigma Delta modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees third-order anti-aliasing filtering.

• 出版日期2015-3