Area-efficient and ultra-low-power architecture of RSA processor for RFID

作者：Wang, D M^*; Ding, Y Y; Zhang, J; Hu, J G; Tan, H Z

来源：Electronics Letters, 2012, 48(19): 1185-U31.

DOI：10.1049/el.2012.1767

Presented is an area-efficient and ultra-low-power hardware architecture of a 1024-bit RSA processor using a modified Montgomery algorithm. Since RSA for RFID often offers authentication and data encryption, small area, low power and high speed are its final goal. Proposed is the following progress: 1. to improve the Montgomery algorithm including preprocessing and Montgomery multiplication; 2. to design an architecture by pipelining two parallel multiply-add units using two-port register files; 3. to provide low power design methods. The result is the lowest power architecture of an RSA processor. The design has been fabricated using SMIC 0.13 mu m CMOS technology and the test results show that the proposal design is most suitable for the low power systems.

• 出版日期2012-9-13
• 单位中山大学