Phase-locked loop design with fast-digital-calibration charge pump

作者：Wang San Fu^*; Hwang Tsuen Shiau; Wang Jhen Ji

来源：International Journal of Electronics, 2016, 103(2): 342-354.

DOI：10.1080/00207217.2015.1036371

• phase-locked loop
• charge pump
• fast-digital-calibration
• current mismatch
• lock detector

A fast-digital-calibration technique is proposed for reducing current mismatch in the charge pump (CP) of a phase-locked loop (PLL). The current mismatch in the CP generates fluctuations, which is transferred to the input of voltage-controlled oscillator (VCO). Therefore, the current mismatch increases the reference spur in the PLL. Improving current match of CP will reduce the reference spur and decrease the static phase offset of PLLs. Moreover, the settling time, ripple and power consumption of the PLL are also improved by the proposed technique. This study evaluated a 2.27-2.88GHz frequency synthesiser fabricated in TSMC 0.18m CMOS 1.8V process. The tuning range of proposed VCO is about 26%. By using the fast-digital-calibration technique, current mismatch is reduced to lower than 0.97%, and the operation range of the proposed CP is between 0.2 and 1.6V. The proposed PLL has a total power consumption of 22.57mW and a settling time of 10s or less.

• 出版日期2016-2-1