Design of 512-bit logic process-based single poly EEPROM IP

作者：Jin Li yan; Jang Ji Hye; Yu Yi ning; Ha Pan Bong; Kim Young Hee^*

来源：Journal of Central South University of Technology, 2011, 18(6): 2036-2044.

DOI：10.1007/s11771-011-0939-4

• single poly EEPROM cell
• Fowler-Nordheim tunneling
• logic process
• radio frequency identification
• small area

A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 mu m(2), about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18 mu m logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 mu W, respectively, and the EEPROM size is 0.12 mm(2).

• 出版日期2011-12