Dynamically reconfigurable architecture for symmetric ciphers

作者：Wang, Bo; Liu, Leibo^*

来源：Science China Information Sciences, 2016, 59(4): 042403.

DOI：10.1007/s11432-015-5381-z

• reconfigurable cryptographic architecture
• symmetric cryptography
• algorithm flexibility
• performance
• area efficiency
• energy efficiency

In this paper, a very large scale integration (VLSI) architecture for a reconfigurable cryptographic processor is presented. Several optimization methods have been introduced into the design process. The interconnection tree between rows (ICTR) method reduces the interconnection complexity and results in a small area overhead. The hierarchical context organization (HCO) scheme reduces the total context size and increases the dynamic configuration speed. Most symmetric ciphers, including AES, DES, SHACAL-1, SMS4, and ZUC, can be implemented using the proposed architecture. Experimental results show that the proposed architecture has obvious advantages over current state-of-the-art architectures reported in the literature in terms of performance, area efficiency (throughput/area) and energy efficiency (throughput/power).

• 出版日期2016-4
• 单位清华大学