A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps

作者：Lu Ping^*; Liscidini Antonio; Andreani Pietro

来源：IEEE Journal of Solid-State Circuits, 2012, 47(7): 1626-1635.

DOI：10.1109/JSSC.2012.2191676

• Gated ring oscillator
• time-to-digital converter
• Vernier delay line

Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90 nm CMOS process and consumes 3 mA from 1.2 V when operating at 25 MHz. The native Vernier resolution of the TDC is 5.8 ps, while the total noise integrated over a bandwidth of 800 kHz yields an equivalent TDC resolution of 3.2 ps.

• 出版日期2012-7