A low-power/high-resolution dual-mode analog-to-digital converter for wireless sensor applications

作者：Kim Jae Joon^*; Cho Chang Hyuk; Chae Kwan Yeob; Byun Sangjin

来源：IEICE Electronics Express, 2011, 8(20): 1730-1735.

DOI：10.1587/elex.8.1730

• integrating resolution booster
• successive approximation register
• dual-mode architecture
• wireless sensor

A successive approximation register (SAR) analog-to-digital converter (ADC) with an integrating resolution booster (IRB) is proposed and experimentally verified to provide the capability of dual-mode operation, that is, low-power and high-resolution modes. This dual-mode architecture corresponds to a kind of hybrid ADC architecture, combining a low-power SAR ADC and a high-resolution integrating-type ADC together. A prototype ADC design is fabricated in a 0.18 mu m CMOS process, and its dual-mode operation is experimentally verified. The total power consumption in the low-power mode was only 8 mu W with the resolution of 6 bits, and the high-resolution mode achieved an additional resolution of 4 bits by activating the IRB, consuming the instant power of 380 mu W.

• 出版日期2011-10-25