Multirate Cascaded Discrete-Time Low-Pass Delta Sigma Modulator for GSM/Bluetooth/UMTS

作者：Bos Lynn^*; Vandersteen Gerd; Rombouts Pieter; Geis Arnd; Morgado Alonso; Rolain Yves; Van der Plas Geert; Ryckaert Julien

来源：IEEE Journal of Solid-State Circuits, 2010, 45(6): 1198-1208.

DOI：10.1109/JSSC.2010.2046240

• Cascade
• CMOS
• delta sigma modulation
• multimode
• multirate
• sigma delta modulation

This paper shows that multirate processing in a cascaded discrete-time Delta Sigma modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time Delta Sigma modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded Delta Sigma modulator enables the power efficient implementation of multiple communication standards.
The advantages of multirate cascaded Delta Sigma modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations.
This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time Delta Sigma modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode Delta Sigma modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm(2). Measurement results show a dynamic range of 66/77/85 dB for UMTS/Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ.

• 出版日期2010-6