摘要
This article presents a low power triple-mode parallel-processing CMOS receiver for BD-II/GPS/Galileo joint navigation applications. An innovative image rejecting parallel-processing architecture is proposed, which utilizes a single frequency synthesizer, shares the front-end, and adopts two complex band-pass filters in two channels separately, aiming for the receiving of BD-II B1/GPS L1/GALILEO L1 multistandard navigation signals simultaneously. The proposed triple-mode parallel-processing receiver is fabricated in a 0.18 m CMOS process with 22.2 mA power consumption under the triple-mode parallel-processing navigation. Measured results show that it has a maximum conversion gain of 101.5 dB and a double-side-band noise figure of 3.3 dB with the fixed IF of 7*f(0) (f(0)=1.023 MHz), tunable IF bandwidth of 2*f(0)/4*f(0), and more than 34 dB image rejection.
- 出版日期2013-11
- 单位北京大学; 北京大学深圳研究生院