A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

作者：Chang Wei Sung^*; Huang Po Chun; Lee Tai Cheng

来源：IEEE Journal of Solid-State Circuits, 2014, 49(12): 2964-2975.

DOI：10.1109/JSSC.2014.2359670

• Digital pulse-width modulator (DPWM)
• divider-less
• fractional-N synthesizer
• noise folding
• phase-locked loop (PLL)
• SSPLL

A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. The frequency synthesizer achieves a low in-band phase noise of 112 dBc/Hz at a 2.3 GHz output frequency. The analysis for the frequency synthesizer, especially for the nonlinear characteristics of the circuits, is proposed. Fabricated in a 0.18 mu m CMOS technology, the frequency synthesizer consumes 9.6 mA and achieves figure-of-merit of -239.1 dB, corresponding to 266 fs rms jitter.

• 出版日期2014-12
• 单位中国科学院电工研究所