A-244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique

作者：Ikeda Sho^*; Ito Hiroyuki; Kasamatsu Akifumi; Ishikawa Yosuke; Obara Takayoshi; Noguchi Naoki; Kamisuki Koji; Yao Jiyang; Hara Shinsuke; Dong Ruibing; Dosho Shiro; Ishihara Noboru; Masu Kazuya

来源：IEEE Journal of Solid-State Circuits, 2017, 52(4): 1123-1133.

DOI：10.1109/JSSC.2016.2637001

• CMOS
• digital calibration
• frequency reference
• phase-locked loop (PLL)
• piezoelectric resonator (PZR)

This paper proposes a cascaded fractional-N phase-locked loop (PLL) based on a high-frequency piezoelectric resonator (PZR). Sub-ppb-order frequency resolution is achieved by a channel adjustment technique. Besides its small form factor, a high-Q PZR at gigahertz frequencies realizes a very low phase-noise synthesizer for RF applications. However, three fundamental issues remain to be solved: the narrow tuning range and large process variation of PZR-based oscillators, the low-frequency resolution of a PLL referenced to gigahertz-order frequencies, and the undesirable harmonic oscillation caused by the inductance of the CMOS-PZR bonding wire. To overcome these issues, we propose a channel-adjusting technique (CAT) that adaptively sets the division ratio of two PLLs to maintain constant output frequency of the second PLL while varying the PZR oscillator frequency, hence permitting the narrow tuning range and wide process variation of the PZR oscillator. The first PLL in our PLL architecture determines the output frequency resolution and the second reduces the power consumption of the delta-sigma modulator. We also suppress the harmonic oscillations in the PZR oscillator. The prototype PLL is fabricated in a 65-nm CMOS and achieves an 8.484-8.912-GHz output, 180-fs rms jitter, and -244-dB FOM while consuming 12.7-mW power. We developed a cascaded fractional-N PLL based on a high-frequency PZR with a sub-ppb-order CAT, which overcomes the narrow tuning range problem in gigahertz PZRs. A prototype PLL fabricated in a 65-nm CMOS consumed 12.7 mWand output 8.484-8.912 GHz with 180-fs rms jitter.

• 出版日期2017-4