A 2.6-3.4 GHz Fractional-N Sub-Sampling Phase-Locked Loop Using a Calibration-Free Phase-Switching-Sub-Sampling Technique

作者：Liang Zhipeng^*; Yi Xiang; Yang Kaituo; Boon Chirn Chye

来源：IEEE Microwave and Wireless Components Letters, 2018, 28(2): 147-149.

DOI：10.1109/LMWC.2017.2779889

• Calibration free
• CMOS phase-locked loop (PLL)
• fractional-N sub-sampling (SS)
• phase switching (PS)

Sub-sampling phase-locked loop (SSPLL) achieves lower in-band phase noise compared to a conventional charge-pump phase-locked loop with frequency dividers. Recently, several works have been reported to enable fractional-N operation of SSPLL to broaden its applications. However, they require careful calibrations with extra silicon area and adjusting time (similar to 20 ms measured) to achieve low phase noise. For scenarios requiring short settling time such as frequency modulation, such a time consuming calibration is undesirable. This letter presents a phase-switching technique for fractional-N mode SSPLL to eliminate this calibration. The principle of the technique is analyzed and a prototype is fabricated in 65-nm CMOS technology. Even without calibration, the frequency synthesizer achieves a figure of merit of -234.3 dB under fractional-N operation, with 13.3-mW power consumption at 1.2-V supply.

• 出版日期2018-2
• 单位南阳理工学院