A 14-bit 100-MS/s CMOS pipelined ADC with 11.3 ENOB

作者：Wang, Ke^*; Fan, Chaojie; Zhou, Jianjun; Pan, Wenjie

来源：Chinese Journal of Semiconductors, 2013, 34(8): 085015.

DOI：10.1088/1674-4926/34/8/085015

• Capacitor mismatch
• Digital calibrations
• MDAC
• Pipelined ADCs
• Pipelined analog-to-digital converter
• SHA-less
• Signal-to-noise distortion ratio
• Spurious-free dynamic range

This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter (ADC) in 0.18 μm CMOS process with a 1.8 V supply voltage. A fast foreground digital calibration mechanism is employed to correct capacitor mismatches. The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio (SNDR) and an 87.5 dB spurious-free dynamic range (SFDR) with a 30.7 MHz input signal, while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input. The power consumption is 543 mW and a total die area of 3 ×4 mm2is occupied.

• 出版日期2013
• 单位上海交通大学