摘要
An 8-bit single-input successive approximation register (SAR) analog-to-digital converter (ADC) for long term evolution (LTE) system with an internal ring oscillator is implemented. A novel 5-bit resistor and 3-bit capacitor segment digital-to-analog converter (DAC) is used to minimize the chip area. The design was fabricated in a 0.13 mu m CMOS process with an area of 0.1mm(2) and a power of 1.2 mW. The measurement results show that the DNL and INL of the proposed ADC are 0.11/-0.18 LSB and 0.8/-0.04 LSB respectively. The SFDR and SNDR can get 53 dB and 43.3 dB respectively.
- 出版日期2011
- 单位华南理工大学