A 12-b 40-MS/s Calibration-Free SAR ADC

作者：Hsu Chung Wei^*; Chang Soon Jyh; Huang Chun Po; Chang Li Jen; Shyu Ya Ting; Hou Chih Huei; Tseng Hwa An; Kung Chih Yuan; Hu Huan Jui

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 65(3): 881-890.

DOI：10.1109/TCSI.2017.2771364

• High-resolution SAR ADC
• residue oversampling
• capacitor mismatch
• DEM
• calibration-free

This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.

• 出版日期2018-3