A 1-3 GHz Delta-Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI

作者：Gheidi Hamed^*; Nakatani Toshifumi; Leung Vincent W; A**eck Peter M

来源：IEEE Journal of Solid-State Circuits, 2017, 52(5): 1185-1195.

DOI：10.1109/JSSC.2017.2656139

• Delay-locked loop (DLL)
• delta-sigma modulator (DSM)
• digital signal processing
• phase modulator
• tapped delay line

This paper presents a new fully digital architecture for an RF phase modulator with significantly improved phase resolution. The modulator utilizes 32 variable delay-lines in a delay-locked loop (DLL) configuration to provide 1-3 GHz operation with coarse 5-bit resolution. A 5-bit low-glitch multiplexer with accurate delay control on the control lines is used to select different taps of the DLL according to the baseband digital phase data to generate the desired phase modulated signal at the output. To further increase the effective resolution, a high speed 10-bit input, 5-bit output digital delta-sigma modulator (DSM) is added in front of the multiplexer. The DSM compensates for the phase truncation occurring in the 5-bit DLL. The impact of delay mismatch and phase offset in the DLL on the phase modulator output performance are studied. The phase modulator IC is implemented in 45-nm CMOS SOI and achieves <2% rms EVM together with 55-dB rejection of close-to-carrier emissions for an 8-Mb/s GMSK signal at 2.3 GHz, with power consumption below 35 mW.

• 出版日期2017-5