A Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine With Adaptive Data Compression

作者：Zeinolabedin Seyed Mohammad Ali^*; Zhou Jun; Kim Tony Tae Hyoung

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2016, 63(10): 1690-1700.

DOI：10.1109/TCSI.2016.2585657

• Adaptive data compression
• area efficient
• Laplacian pyramid
• power efficient
• ultra-low voltage

This paper proposes a power and area efficient Laplacian Pyramid processing engine (LPPE) for real-time portable image/video processing applications. On the architecture level, an adaptive data compression technique is proposed to reduce the power and area of FIFOs in the LPPE while maintaining small mean square error (MSE). A new filtering extension method is proposed to reduce the output errors caused by image boundary pixels. On the circuit level, near-threshold operation is adopted to further reduce the power consumption. The proposed LPPE is fabricated in 0.18-mu m CMOS process technology and consumes only 452 mu W/frame with a clock frequency of 3.68MHz and 112 frames per second at 0.5 V. The area is reduced by 18.98%-36.06% compared to conventional counterpart.

• 出版日期2016-10
• 单位南阳理工学院