Centaur: a hybrid network-on-chip architecture utilizing micro-network fusion

作者：Lee Junghee^*; Nicopoulos Chrysostomos; Lee Hyung Gyu; Kim Jongman

来源：Design Automation for Embedded Systems, 2014, 18(3-4): 121-139.

DOI：10.1007/s10617-014-9131-z

• Networks-on-chip
• Interconnection networks
• Segregated/separated networks

The escalating proliferation of multicore chips has accentuated the criticality of the on-chip network. Packet-based networks-on-chip (NoC) have emerged as the de facto interconnect of future chip multi-processors (CMP). On-chip traffic comprises a mixture of data and control messages from the cache coherence protocol. Given the latency-criticality of control messages, in this paper we aim to optimize their delivery times. Instead of treating the on-chip router as a monolithic component, we advocate the introduction of an ultra-low-latency ring-inspired (i.e., utilizing ring primitive building blocks) support micro-network that is optimized for control messages. This NoC is fused with a throughput-driven conventional NoC router to form a hybrid architecture, called Centaur, which maintains separate data paths and control logic for the two fused networks. Full-system simulation results from a 64-core CMP indicate that the proposed fused Centaur router improves overall system performance by up to 26 %, as compared to a state-of-the-art router implementation. Furthermore, hardware synthesis results using commercial 65 nm libraries indicate that Centaur%26apos;s area and power overheads are 9 and 3 %, respectively, as compared to a baseline router design. More importantly, the new design does not affect the router%26apos;s critical path.

• 出版日期2014-9