Aggressive drowsy cache cells

作者：Shawkey H A; El Dib D A^*; Abid Z

来源：International Journal of Electronics, 2010, 97(1): 105-118.

DOI：10.1080/00207210903168330

• drowsy caches
• low leakage
• cache cells
• aggressive drowsy
• low-voltage supply

An aggressive drowsy cache block management, where the cache block is forced into drowsy mode all the time except during write and read operations, is proposed. The word line (WL) is used to enable the normal supply voltage (V(DD_ high)) to the cache line only when it is accessed for read or write whereas the drowsy supply voltage (V(DD_ low)) is enabled to the cache cell otherwise. The proposed block management neither needs extra cycles nor extra control signals to wake the drowsy cache cell, thereby reducing the performance penalty associated with traditional drowsy caches. In fact, the proposed aggressive drowsy mode can reduce the total power consumption of the traditional drowsy mode by 13% or even more, depending on the cache access rate, access frequency and the CMOS technology used.

• 出版日期2010