A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors

作者：Kansakar Prasanna^*; Munir Arslan

来源：IEEE Transactions on Parallel and Distributed Systems, 2018, 29(1): 2-15.

DOI：10.1109/TPDS.2017.2745580

• Multicore/manycore processors
• processor design parameters
• design space exploration
• cycle-accurate simulator (ESESC)
• PARSEC and SPLASH-2 benchmarks
• parameter optimization

The need for application-specific design of multicore/manycore processing platforms is evident with computing systems finding use in diverse application domains. In order to tailor multicore/manycore processors for application specific requirements, a multitude of processor design parameters have to be tuned accordingly which involves rigorous and extensive design space exploration over large search spaces. In this paper, we propose an efficient methodology for design space exploration. We evaluate our methodology over two search spaces small and large, using a cycle-accurate simulator (ESESC) and a standard set of PARSEC and SPLASH-2 benchmarks. For the smaller design space, we compare results obtained from our design space exploration methodology with results obtained from fully exhaustive search. The results show that solution quality obtained from our methodology are within 1.35 - 3.69 percent of the results obtained from fully exhaustive search while only exploring 2.74 - 3 percent of the design space. For larger design space, we compare solution quality of different results obtained by varying the number of tunable processor design parameters included in the exhaustive search phase of our methodology. The results show that including more number of tunable parameters in the exhaustive search phase of our methodology greatly improves solution quality.

• 出版日期2018-1-1