Design of an On-Chip Balun With a Minimum Amplitude Imbalance Using a Symmetric Stack Layout

作者：Hsu Heng Ming^*; Huang Jhao Siang; Chen Szu Yuan; Lai Szu Han

来源：IEEE Transactions on Microwave Theory and Techniques, 2010, 58(4): 814-819.

DOI：10.1109/TMTT.2010.2041590

• Balun
• couple line
• imbalance
• on-chip

This study develops a compact balun layout to minimize amplitude imbalance. Three baluns with different metal layers are fabricated using 0.13-mu m CMOS technology and their imbalance performance evaluated. Measurement made using eight metal layers in coil windings at a particular layout reveal that the proposed device exhibits minimal amplitude and phase imbalance of 0.2 dB and +/-0.5 degrees with a chip outer dimension of 100 mu m.

• 出版日期2010-4