A 12.5-bit 4 MHz 13.8 mW MASH Delta Sigma Modulator With Multirated VCO- Based ADC

作者：Zaliasl Samira^*; Saxena Saurabh; Hanumolu Pavan Kumar; Mayaram Kartikeya; Fiez Terri S

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2012, 59(8): 1604-1613.

DOI：10.1109/TCSI.2012.2206506

• Analog to digital conversion
• delta-sigma
• MASH architecture
• multirate MASH modulator
• VCO-based quantizer

A novel MASH delta-sigma (Delta Sigma) ADC architecture is introduced that has a multirated voltage controlled oscillator (VCO)-based ADC in its second stage. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. A prototype consists of a first-order switched-capacitor (SC) modulator operating at 100MHz in the first stage followed by a second-stage VCO-based ADC operating at 1.2 GHz. A custom IC prototype of this architecture achieves 77.3 dB signal-to-noise-ratio (SNR) over a 4 MHz signal bandwidth with a power consumption of 13.8 mW. It was fabricated in a 130 nm 1P8M CMOS process. The resulting FoM is 298 fJ per conversion.

• 出版日期2012-8