A 0.5 V Operation V-TH Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems

作者：Tanakamaru Shuhei^*; Takeuchi Ken

来源：IEEE Journal of Solid-State Circuits, 2011, 46(10): 2406-2415.

DOI：10.1109/JSSC.2011.2163355

• Charge pump
• DRAM
• low power
• SRAM
• word-line booster

A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. To realize the low power LSIs it is important to decrease the supply voltage (V-DD) to e.g., 0.5 V because the active power consumption of LSIs strongly depends on V-DD. When the 0.5 V V-DD is adopted, widely used RAM, SRAM is difficult to operate because the SRAM is sensitive to the V-TH variation. DRAM has a potential to operate at such low V-DD. As the key technology to realize 0.5 V operation DRAM, this paper proposes the word-line booster circuit. The theoretical equation of the output voltage and the energy consumption of the proposed booster is extensively investigated. The proposed booster outputs 1.4 V in 3 clock cycles, which is shorter than the DRAM access time and the power consumption is 60 pJ. 1.4 V is the required word-line voltage to successfully charge the DRAM cell capacitor. Compared with the conventional boosters, the rising time and the power consumption are decreased to 38% and 68%, respectively, with the same circuit area. The proposed circuit was fabricated with the 0.18 mu m standard CMOS process and the high-speed boosting is experimentally demonstrated.

• 出版日期2011-10