A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL)

作者：Balcioglu Yalcin^*; Dundar Gunhan

来源：Integration, the VLSI Journal, 2017, 58: 142-154.

DOI：10.1016/j.vlsi.2017.04.001

• All-digital phase locked loop
• High-level synthesis
• Phase domain model
• Phase noise estimation

In this paper, we present a new approach that provides a complete design, analysis, and high-level synthesis (HLS) flow for all-digital phase locked loops (ADPLL). CellPLL uses a methodology for direct design of transfer functions given a set of specifications by the user. In order to analyze the estimated phase noise of each design, a flexible phase domain model implementation of ADPLL is incorporated. For automatic design implementation, a new HLS engine with a library parser and ADPLL realization template is used. The flow is applied for four different cases and the results match circuit level simulation results. CellPLL successfully generates ADPLL designs and provides ability to move between production processes.

• 出版日期2017-6