摘要
A very simple, wide range and programmable pulse width controller or duty cycle corrector (DCC) is presented. Simulating the circuit in 0.35 mu m Complementary MOSFET (CMOS) technology shows that the frequency range of the input signal can be within 250 MHz to 1.6 GHz, with a duty cycle of 30-70%. The proposed circuit generates an output signal with programmable duty cycle in the range of 30-70% with steps of 10% which could be extended to more steps by simple variations. The systematic peak-to-peak jitter at center frequency (1 GHz) is 1ps, while adding a random noise source of 5% of the power supply, increases it to 13 ps. the power consumption at maximum speed (1.6 GHz) is 4.9 mW. MonteCarlo simulations show maximum of 3.4% error at the 1.5 GHz input frequency and 70% output duty cycle.
- 出版日期2014-5