A 2.25-2.7 GHz Area-Efficient Subharmonically Injection- Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop

作者：Tseng Yen Hsiang; Yeh Che Wei; Liu Shen Iuan^*

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64(4): 811-822.

DOI：10.1109/TCSI.2016.2620151

• Correlation loop
• correlator
• digital-to-time converter (DTC)
• fractional-N
• frequency synthesizer
• phase-locked loop (PLL)
• subharmonically injection-locked technique

An area-efficient subharmonically injection-locked fractional-N frequency synthesizer is presented. The phase domain analysis confirms that a second-order subharmonically injection-locked phase-locked loop (SIPLL) can be stable even if the loop filter is composed of only a tiny capacitor. Thus, the area of the loop filter shrinks dramatically to realize an areaefficient SIPLL. Besides, a fast-converging correlation loop is used to calibrate the gain error of the digital-to-time converter in background by using a binary search algorithm. It ensures the initial output of the correlator close to the final one and is insensitive to process/supply/temperature variations. The chip is fabricated in a 40 nm process and occupies a core area of 0.0104 mm(2). The converging time of the correlation loop is within 30 mu s. The power consumption is 3.19 mW from a 1.1 V supply.

• 出版日期2017-4
• 单位中国科学院电工研究所