An Area Efficient Real-Time PFFT Architecture Using Parallel Distributed Arithmetic

作者：Ling, Xiaofeng; Gong, Xinbao^*; Zang, Xiaogang; Jin, Ronghong

来源：IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2012, E95A(2): 600-603.

DOI：10.1587/transfun.E95.A.600

• discrete Fourier transform (DFT)
• prime factor Fourier transform
• parallel distributed arithmetic
• cyclic convolution

In this letter, an area-efficient architecture for the hardware implementation of the real-time prime factor Fourier transform (PFFT) is presented. In the proposed architecture, a prime length DFT module with the one-point-per-cycle (OPPC) property is implemented by the parallel distributed arithmetic (DA), and a cyclic convolution feature is exploited to simplify the structure of the DA cells. Based on the proposed architecture, a real-time 65-point PFFT processor is designed, and the synthesis results show that it saves over 8% gates compared to the existing real-time 64-point DFT designs.

• 出版日期2012-2
• 单位上海交通大学